There has developed a substantial need for a digital counting system which can be used for counting or timing. When timing, the input pulses to the system have a known time base frequency so that by counting the pulses a timing operation is obtained. In these systems, it is desirable, when timing, to provide a readout in tenths or hundredths of a second. Since the time base frequency most commonly available is line frequency of 60 cycles per second, or the rectified 120 pps, timing in hundredths of a second has been somewhat difficult. Originally, to obtain these portions of a second, the 60 cycle line frequency was multiplied and divided in complex digital circuits which required a substantial amount of space on an LSI chip. These arrangements have been unsatisfactory. Thus, the programmable controller for 5/6 operations was developed and is set forth in prior U.S. Pat. Nos. 3,789,195 and 3,867,614. This type of system passes five out of six pulses from the incoming pulse to the counter. In this manner, if a full wave rectifier is used to produce 120 pps, 100 pulses can be created at the counter during each second. This provides a convenient, simplified system for producing fractional timing using a digital counter.
As disclosed in prior application Ser. No. 478,979 filed June 13, 1974, there has been developed a demand for a counting and timing system which can be used to totalize either time or counts. In this type of system, a combined up/down digital counter is employed which counts or times one direction when receiving pulses from a first input and in the other direction when receiving pulses from a second input. By dividing these input pulses with a 5/6 control, the counter can totalize time by recording time on one input terminal and time on another input terminal in a subtractive mode. In the past, the systems for passing five pulses out of six has included an arrangement wherein the sixth pulse is dropped or inhibited out of each group of six incoming pulses. By employing this type of system, when timing in two different directions, it is possible to reverse the timing directions at the time when an inhibit signal is created. When this happens, the time in the opposite direction does not actually track exactly the time in the first direction. This can cause an error of 8.33 ms in totalizing time using a 5/6 system, as disclosed in the prior patents and application. The present application relates to an improvement when totalizing time using a 5/6 circuit, wherein the timing in both directions exactly tracks each other so that the inhibit signal in either counting direction occurs at the same progressively totalized count position or positions. In other words, when counting in the first direction if the inhibit signal occurs on the sixth pulse, when counting down or in the other direction, the inhibit signal occurs at the same location on the progressive counting cycle. Assume that timing in one direction requires seven pulses causing the counter to record the number six. When counting in the other direction from the number six, the inhibit signal will occur on the second pulse. In the past, the inhibit signal would have occurred again on the sixth pulse in the opposite direction which would prevent tracking in both directions when in the 5/6 timing mode. By using the present invention, tracking in both directions is assured so that the inhibit signal occurs at the same progressively totalized count position to eliminate the previous possible error of 8.33 ms.
In the past, the only suggestion for decreasing the possible error when totalizing time in the 5/6 mode has been to increase the frequency of the counting pulses. For instance, if the timing pulses were increased to 240 pps, a possible error of only 4.17 ms could occur. This error still is unsatisfactory in some operations, but it is less than normally experienced. By again multiplying the incoming pulses, the error can be progressively reduced. However, multiplying circuits at the input of the timing system are expensive and require a substantial increase in components. In addition, the counter must have higher capacity to handle the higher frequency. Thus, the present invention is a substantial improvement over the prior system without requiring the expense of multiplication circuitry and higher capacity digital counting circuits.